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18-bit, 2.5 lsb inl, 570 ksps sar adc ad7679 rev. 0 in fo rmation fur n ished by an al o g d e v i c e s is believed t o be accurate an d r e liable. how e ver, no r e spon sibili ty is assumed by anal og de vices fo r its use, nor for a n y i n fri n geme nt s of p a t e nt s or ot h e r ri g h t s o f th ird parties that m a y res u lt fro m its use . s p ecificatio n s subj ec t to chan ge witho u t n o tice. no licen s e is g r an te d b y implicatio n or ot h e rwi s e u n de r any p a t e nt or p a t e nt ri ght s of a n al og de vi c e s. tra d emark s a n d registered tra d ema r ks are the proper ty of th eir respectiv e co mpan ies. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . features 18-bit resolut i on with no missing codes no pipeline de l a y (sar archite c ture) differentia l inp u t range: v re f (v re f up to 5 v) throughput: 570 ksps inl: 2.5 lsb max (9.5 ppm of full scale) dynamic range : 103 db typ ( v re f = 5 v) s/(n+d): 100 d b typ @ 2 kh z ( v re f = 5 v) parallel (18-,16-, or 8-bit bus) and seria l 5 v/3 v interf ace spi ? /qsp i ? /mi c rowire ? /ds p compatible on-board reference buffer single 5 v supp ly operation power dissipati o n: 76 mw @ 5 00 k s ps 150 w @ 1 ks ps 48-lea d lqfp or 48-l ead lfcs p package pin-to-pin compatible up grad e of ad 7674/a d 7676/a d 76 78 applic ati o ns ct scanners high dynamic data acq u isitio n geophone and hydrophone sensors -? replacement (low power, multichannel) instrumentation spectrum anal ysis medical instr u ments general description the ad7679 is a n 18-b i t, 570 ks ps, c h a r g e r e dis t r i b u tion sar , f u l l y dif f er en t i al a n alog-t o-dig i t a l co n v er t e r t h a t o p era t e s o n a s i ng l e 5 v p o we r su p p ly . the p a r t c o n t ains a hig h sp e e d 1 8 -bi t s a m p ling ad c, a n in t e r n al con v ersio n c l o c k, an in t e r n al re f e re nc e bu f f e r , e r ror c o r r e c t i o n c i rc u i t s , a n d b o t h s e r i a l a n d p a ral l e l sys t em i n t e r f ace p o r t s. the p a r t is a v a i l a b l e in a 48-lead l q fp o r 48-lead lfcs p wi th o p era t ion sp e c if ie d f r o m C40 c t o +85c. func tio n a l block di agram switched cap da c 18 control logic and calibration circuitry clock ad7679 d[17:0] busy rd cs mode0 ognd ovdd dgnd dvdd avd d agnd ref refgnd in+ in? pd reset seria l port parallel interfac e cnvst pdbu f refbufi n mode1 03085 ?0?001 f i gur e 1 . f u nctio n al bl oc k dia g r a m table 1. pulsa r selection t y p e / k s p s 1 0 0 C 2 5 0 5 0 0 C 5 7 0 800C 1000 pseudo- differential ad7651 ad7660 / ad766 1 ad7650 / ad765 2 ad7664 / ad766 6 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 AD7674 multichannel / simultaneous ad7654 ad7655 product highlights 1. h i g h res o l u tion, f a s t thr o ug h p u t . the ad7679 is a 570 ks ps, c h arg e r e dis t r i b u tion, 18-b i t sar ad c ( n o l a t e n c y). 2. e x ce l l en t a c c u r a c y . the ad7679 has a maxim u m in t e g r al n o nlin ea r i ty o f 2.5 ls b wi th n o mis s in g 18-b i t co des. 3 . se ri al o r p a r a ll e l i n t e rf a c e . v e rs a t ile p a ral l el (18-, 16-, o r 8-b i t b u s) o r 3-wir e s e r i al in t e r f ace a r ra n g em e n t com p a t ib le w i t h b o t h 3 v a nd 5 v log i c.
ad7679 rev. 0 | page 2 of 2 8 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 7 pin configuration and functional descriptions .......................... 8 definition of specifications ........................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 15 converter operation .................................................................. 15 typical connection diagram ................................................... 17 power dissipation versus throughput .................................... 19 conversion control ................................................................... 19 digital interface .......................................................................... 20 parallel interface ......................................................................... 20 serial interface ............................................................................ 20 master serial interface ............................................................... 21 slave serial interface .................................................................. 22 microprocessor interfacing ...................................................... 24 application hints ........................................................................... 25 layout .......................................................................................... 25 evaluating the ad7679s performance .................................... 25 outline dimensions ....................................................................... 26 ordering guide ............................................................................... 26 revision history revision 0: initial version
ad7679 rev. 0 | page 3 of 28 specifications table 2. C40c to +85c, v ref = 4.096 v, avdd = dvdd= 5 v, ovdd = 2. 7 v to 5.25 v, unless otherwise noted. parameter conditions min typ max unit resolution 18 bits analog input voltage range v in+ C v inC Cv ref +v ref v operating input voltage v in+ , v inC to agnd C0.1 avdd+0.1 v analog input cmrr f in = 100 khz 68 db input current 570 ksps throughput 25 a input impedance 1 throughput speed complete cycle 1.75 s throughput rate 0 570 ksps dc accuracy integral linearity error C2.5 +2.5 lsb 2 differential linearity error C1 +1.75 lsb no missing codes 18 bits transition noise v ref = 5 v 0.7 lsb zero error, t min to t max 3 C40 +40 lsb zero error temperature drift 0.5 ppm/c gain error, t min to t max 3 C0.048 see note 3 +0.048 % of fsr gain error temperature drift 1.6 ppm/c power supply sensitivity avdd = 5 v 5% 4 lsb ac accuracy f in = 2 khz, v ref = 5 v 101 db 4 v ref = 4.096 v 97.5 99 db f in = 10 khz, v ref = 4.096 v 98 db signal-to-noise f in = 100 khz, v ref = 4.096 v 97 db dynamic range v in+ = v inC = v ref /2 = 2.5 v 103 db f in = 2 khz 120 db f in = 10 khz 118 db spurious-free dynamic range f in = 100 khz 105 db f in = 2 khz C115 db f in = 10 khz C113 db total harmonic distortion f in = 100 khz C98 db f in = 2 khz, v ref = 4.096 v 98 db signal-to-(noise + distortion) f in = 2 khz, C60 db input 40 db C3 db input bandwidth 26 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 250 ns overvoltage recovery 250 ns reference external reference voltage range ref 3 4.096 avdd + 0.1 v ref voltage with reference buffer refbufin = 2.5 v 4.05 4.096 4.15 v reference buffer input voltage range refbufin 1.8 2.5 2.6 v refbufin input current C1 +1 a ref current drain 570 ksps throughput 235 a
ad7679 p a r a m e t e r c o n d i t i o n s m i n t y p m a x u n i t digital inpu ts logic levels v il C 0 . 3 + 0 . 8 v v ih 2.0 dvdd + 0.3 v i il C 1 + 1 a i ih C 1 + 1 a digital outpu t s data format 5 pipeline delay 6 v ol i sin k = 1.6 ma 0.4 v v oh i sou r ce = C500 a ovdd C 0.6 v power suppli e s specified performance a v d d 4 . 7 5 5 5 . 2 5 v d v d d 4 . 7 5 5 5 . 2 5 v ovdd 2.7 dvdd + 0.3 7 v operating curre nt 500 ksps throughput a v d d p d b u f h i g h 1 0 . 8 m a dvdd 8 4 . 5 m a ovdd 8 5 0 a pdbuf high @ 5 00 ksps 76 90 mw pdbuf high @ 1 ksps 150 w power dissip a t ion 8 pdbuf low @ 5 00 ksps 89 103 mw tempe r atu r e range 9 specified performance t mi n to t max C 4 0 + 8 5 c 1 se e sect ion . an alog in put s 2 lsb means l e ast si gnificant bit. with t h e 4.096 v input r a nge, 1 lsb is 31.25 v. 3 s e e section. the nominal gain error is not center e d at zer o and is +0 .273% of fsr. this specifica tion is the deviation f r om this n o minal val u e . thes e s p e c i f icatio ns d o no t includ e the e r ro r co ntributio n f r o m the e x te rnal ref e re nce , but d o incl ude the e rror co ntrib ution from the re fer e nce bu ffe r if use d . d e f i n i t i o n o f specifications 4 a l l speci f i c a t i o n s i n db a r e re ferr ed t o a fu ll- sca l e i n put , f s . test ed wi t h a n i n put si gn a l a t 0.5 db below fu ll sca l e un le ss ot h e rwi s e sp eci f i e d. 5 p a r a ll el or se r ial 18-b it. 6 c o nvers i on res u l t s are avail abl e imme d iatel y af ter comp leted c o nvers i on. 7 the max s h ould be the minimu m of 5.25 v and dvdd + 0.3 v. 8 tes t ed in p a ral l el read ing mode. 9 c o ntact f a cto r y f o r e x te nde d te mpe r ature range . rev. 0 | page 4 of 2 8
ad7679 timing specifications t . 0 c t 85c, a d d d d d 5 , o dd 2. 7 t 5.25 , ti t . p t s m i t m u i t r t fi 2 fi ct pi t t 1 1 0 ti t c i t 2 1 . 7 5 cnst lo t busy h i gh d t 5 busy high a m et mt si r t ct t 1 . 5 at d t 5 2 e ci t busy lo d t 6 1 0 ci ti t 7 1 . 5 aiiti ti t 8 2 5 0 reset pi t t 9 1 0 r t fi , fi 5, fi 6 p it m cnst lo t dt i d t 10 1 . 5 dt i t busy lo d t 11 2 0 b a r t t dt i t 12 5 b rii t i t 1 5 1 5 r t fi 8 fi 9 m t si it m 1 cs lo t sync i d t 1 10 cs lo t it scl i d t 15 10 cs lo t sdout d t 16 10 cnst lo t sync d t 17 525 sync at t scl fit e d 2 t 18 it scl pi 2 t 19 25 0 it scl high 2 t 20 12 it scl lo 2 t 21 7 sdout i st ti 2 t 22 sdout i h t i 2 t 2 2 scl lt e t sync d 2 t 2 cs high t sy nc hi- t 25 10 cs high t i t scl hi- t 26 1 0 cs high t sdou t hi- t 27 10 busy high i m t si r t ct 2 t 28 s t cnst lo t sync a t d t 29 1.5 sync dt t busy lo d t 0 25 r t fi 0 fi 1 s si i t m et scl s t ti t 1 5 et scl ati e t sd out d t 2 1 8 sdin st ti t 5 sdin h ti t 5 et scl pi t 5 2 5 et scl high t 6 1 0 et scl lo t 7 1 0 1 i i it , t syn c , scl, sdout tii i it i c l 10 f ti , t i 60 f i. 2 i si m t r i c t . s si m t r t c t . t r. 0 p 5 2 8
ad7679 t . si ck tii i mt r t c t d i s c l 1 0 0 1 1 d i s c l 0 s 0 1 0 1 u i t sync t scl fi t e d mii t 18 1 7 1 7 1 7 it scl pi mii t 19 2 5 6 0 1 2 0 2 0 it scl pi mi t 19 0 8 0 1 6 0 2 0 it scl high mii t 20 1 2 2 2 5 0 1 0 0 it scl lo mii t 21 7 2 1 9 9 9 sdout i st ti mii t 22 1 8 1 8 1 8 sdout i h ti mii t 2 2 0 8 9 scl lt e t sync d mii t 2 6 0 1 0 0 0 b hi it mi t 28 2 . 2 5 . 5 7 . 5 r. 0 p 6 2 8
ad7679 absolute maximum ratings table 5. ad76 79 absolute maximum ratings 1 p a r a m e t e r r a t i n g analog inputs in+ 2 , in? 2 , ref, refbufin, refgnd to agnd avdd + 0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgn d, ognd 0.3 v supply voltages avdd, dvdd, ovdd ?0.3 v to +7 v avdd to d v dd, avdd to ovdd 7 v dvdd to ovdd ?0.3 v to +7 v digital inputs ?0.3 v to dv dd + 0.3 v internal power dissip a tion 3 7 0 0 m w internal power dissip a tion 4 2 . 5 w junction tempe r ature 150c storage temperature range ?65c to +150c lead temperature range (sol dering 10 s e c) 300c 1 st res s es a b ove t h o s e li st ed un der ab so lut e ma xi m u m r a t in gs m a y ca us e permanent d amage to the d e vice. this is a s t ress rating onl y; functional o p e r atio n o f the device at the s e o r any o the r co nd itio ns a b o v e tho se i n di ca t e d i n t h e op era t i o n a l sect i o n of this s p ecif ication is not impl i ed . expos ure t o a b s o lu t e m a x imum rating co nd itio ns fo r e x tend e d pe riod s may af f e ct d e vice rel iabil ity. 2 see an s e ct i o n . a l o g in put s 3 specif ication is f o r d e vice in f r ee air: 4 8 -lead lqfp : ja = 91c/w, jc = 30c/w. 4 speci f i c a t i o n i s fo r devi ce i n fre e a i r: 4 8 - l ea d lfc s p: ja = 26c/w. t o output pin c l 60pf 1 500
ad7679 r. 0 p 8 2 8 pin conf iguration and fu nctional descri ptions 6 5 2 1 0 29 28 27 26 25 1 1 1 5 16 17 1 8 19 20 21 22 2 2 1 2 5 6 7 8 9 10 11 12 8 7 6 5 9 8 7 2 1 0 pi n 1 i d e n ti fi e r to p i e n t t s a gnd cnst pd reset cs rd dgnd a gnd a d d mode0 mode1 d0ob2c nc nc nc n o c o nne ct d1a0 d2a1 d ddiscl0 bu s y d17 d16 d15 ad7679 d5discl1 d1 p dbuf a dd re fbufin nc agnd in nc nc nc in re fgnd re f d6 e x t i nt d 7 in syn c d8inscl d9 rdcs d in ognd o dd d dd dgnd d 10sd ou t d 11sc l d 12syn c d1 rde rr or 0085 0 00 f i . 8-l l fpst - 8 8 - l lfcs p c p - 8 t 6. pi f t i d i t i pi n. mi t 1 d i t i 1, agnd p a p g pi. 2, 7 add p it a p pi. ni 5 . mode0 di dt ott i t m s ti. mode1 di dt ott it m s ti it mo de mo de1 mo de0 diti 0 0 0 1 8 - b i t i t 1 0 1 1 6 - b i t i t 2 1 0 b t i t 1 1 s i i t 5 d0ob2c dio mode 0 18-it it , ti i i bit 0 t t t tt t t i i tit i. i t , t i i i tit ii t t. ob 2c i high , t iit t t i t it i lo , t msb i it, ti i t t tt it it it it. 6, 7, 0 2, 5 n c n c t . 8 d 1 a 0 d i o mode 0 18-it it , ti i i bit 1 t t t tt . i t , t i it i t t i i t i tt, i t 7. 9 d 2 a 1 d i o mode 0 1 18-it 16-it it , ti i i bit 2 t t t tt . i t , ti i t i t t i i t i t t, i t 7. 1 0 d d o i t m o de , ti tt i bit t t t tt . t i i i tt, t it . 11, 12 d5 discl01 dio i t m o de , t i bit bit 5 t t t tt . mode i , ext int i lo, rdcsdin i l o i t t t, t i t, t t i t, t , i i , t it i k tt k t t t t. i t i , t i t . 1 d 6 extint dio i t m o de , t i tt i bit 6 t t t tt . mode i , ti i t, t t i t, i iit t it i t it t k t t k. it ext int ti lo, t it k i t t scl tt. i t ext int t t i high, t t t i i t t k i t t t scl it.
ad7679 pin no. mnemonic type 1 d e s c r i p t i o n 1 4 d 7 or invsync di/o in all mod e s e x c e pt m o de = 3, t h is output is used as bit 7 of the parallel p o rt data output bus. when mode = 3 (s erial mode), this in put, part of the serial port, is us ed to selec t the active state of the sync signal. when low, sync is active high. w h en high, sync is active low. 1 5 d 8 or invsclk di/o in all mod e s e x c e pt m o de = 3, t h is output is used as bit 8 of the parallel p o rt data output bus. when mode = 3 (s erial mode), this in put, part of the serial port, is us ed to invert the sclk signal. it is active in both m a ster and slav e mode. 1 6 d 9 or rdc/sdin di/o in all mod e s e x c e pt m o de = 3, t h is output is used as bit 9 of th e parallel p o rt da ta output bus. when mode = 3 (s erial mode), this in put, part of the serial port, is used as either an externa l data input or a read mode selection inp ut depending on the state of ext / int . when ext/ int is high, rdc/ sdin could be used as a data input to daisy - chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 18 sclk periods after the initiation of the read sequence . when ext/int is l o w, rdc/sdin i s used to select the read mode. when rdc/sdin is high, the data i s output on sd out during conversion. wh en rdc/sdin is low, the data ca n be output on sdout only whe n the conversi o n is comp lete. 17 ognd p input/ output in terface digital power ground. 1 8 o v d d p output interfac e digital power. nominally at the same su pp ly a s the host interface (5 v or 3 v). should not exceed dvdd by more than 0.3 v. 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power gr ound. 2 1 d 1 0 or sdout do in all mod e s e x c e pt m o de = 3, t h is output is used as bit 10 of th e parallel p o rt data output bus. when mode = 3 (s erial mode), this output, part of the serial port, is used as a serial data output synchroni z ed to sclk. conversi on results are stor ed in an on-chip register. the ad7679 provides the conver sion re sult, msb first, from its internal shift register. the data format is determined by the logic level of o b /2c . in serial mode when ext/ int is low, sdout is valid on both edges of sclk. in serial mode when ext/int is high and in vsclk is low, sdout is updated on the sclk rising edge and is valid on the next falling edge; if invsclk is high , sdout is updated on the sc lk falling edge and is valid on the next rising edge. 2 2 d 1 1 or sclk di/o in all mod e s e x c e pt m o de = 3, t h is output is used as bit 11 of th e parallel p o rt data output bus. when mode = 3 (s erial mode), this pin, part of the s e ria l port, is used as a seria l data clock in put or output, depend ent upon the logic state of the ext/ int pin. the ac tive edge where the data sdou t is updated depends upon the logi c state of the invsclk pin. 2 3 d 1 2 or sync do in all mod e s e x c e pt m o de = 3, t h is output is used as bit 12 of th e parallel p o rt data output bus. when mode = 3 (s erial mode), this output, part of the serial port, is used as a digital output fra m e synchronization for use with th e internal data clock (ext/ i nt = logic low). when a read sequence is initiated and invsync is low, s y nc is driven high and remains high while the sdout output i s valid. when a re ad sequence is i n itiated and invs ync is high, s y nc is driven low and remains low while sdout ou tput is valid. 2 4 d 1 3 or rderror do in all mod e s e x c e pt m o de = 3, t h is output is used as bit 13 of th e parallel p o rt da ta output bus. in mode = 3 (s e r ial mode) and w h en ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, whe n a data read is started an d not complete when the follo wing con v e r sion is c o mp lete, the current da ta is lost and rderror is pulsed high. 2 5 C 2 8 d [ 1 4 : 1 7 ] d o bit 14 to bit 17 o f the parallel port data output bus. these pins ar e always outputs regard less of the interface mode. 2 9 b u s y d o busy output. tr ansitions high when a conversi on is started. remain s high until the conversion is complete and the data is latched into the on-chip shift registe r. the falling edge of busy could be used as a data ready clock sign a l . 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface para llel or ser i al output bus is enabled . 32 cs di chip select. when cs and rd are both low, the interface para lle l or serial output bus is enabled. cs is also used to gate the ex ternal clock. 3 3 r e s e t d i reset input. when set to a logic high, reset the ad7679. curren t conversion, if any, is aborted. if not used, this pin could be tied to d g nd. 3 4 p d d i power-down input. when set t o a logic high, pow er c o nsump t ion is reduced and conversion s are inhibited after the current one is completed. rev. 0 | page 9 of 2 8
ad7679 pi n. mi t 1 d i t i 5 cnst di stt ci. i cnst i hig h t iiti t 8 i t, t t i cnst t t it it t tt iitit i. i cnst i lo t iiti i t , t it i t it t tt i i tt iit. 6 agnd p mt b ti t a g. 7 r e f a i r it t it r b ott. a t ti i i t it i t . s ti it itt t it . 8 refgnd ai r it a g. 9 in ai diti nti a it. in ai diti piti a it. 6 r e f b u f i n a i r b it t. t it i i. it tt .096 ti 2 . 5 i i ti i. 8 p d b u f d i a ci bi r . lo , i t. hig h , i it . 1 ai a i t ao a ot t d i d i i t i t d io bi i t i d i i t d o d i i t ot t p p . t 7. dt b i t di i ti mo d e m o d e 1 mo d e 0 d 0 o b 2c d 1 a 0 d 2 a 1 d d 9 d1011 d1215 d 1 6 1 7 d i t i 0 0 0 r 0 r 1 r 2 r r 9 r 1 0 1 1 r 1 2 1 5 r 1 6 1 7 1 8 - b i t p 1 0 1 ob 2 c a 0 0 r 2 r r 9 r 1 0 1 1 r 1 2 1 5 r 1 6 1 7 1 6 - b i t hi 1 0 1 ob 2 c a01 r0 r1 a 16-bit l 2 1 0 ob 2 c a00 a10 a hi- r1011 r1215 r1617 8-bit high bt 2 1 0 ob 2 c a00 a11 a hi- r2 r7 r89 8-bit mid bt 2 1 0 ob 2 c a01 a10 a hi- r01 a 8-bit lo bt 2 1 0 ob 2 c a01 a11 a hi- a r01 8-bit lo bt 1 1 ob 2 c a hi- si it si it r017 i t 18 -it adc t i it tt it. r. 0 p 10 28
ad7679 rev. 0 | page 11 of 28 definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. gain error the first transition (from 00000 to 00001) should occur for an analog voltage ? lsb above the nominal Cfull scale (C4.095991 v for the 4.096 v range). the last transition (from 11110 to 11111) should occur for an analog voltage 1? lsb below the nominal full scale (4.095977 v for the 4.096 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. zero error the zero error is the difference between the ideal midscale input voltage (0 v) from the actual voltage producing the midscale output code. spurious-free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input, and is expressed in bits. it is related to s/(n+d) by the following formula: enob = ( s/[ n + d ] db C 1.76)/6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. dynamic range dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response transient response is the time required for the ad7679 to achieve its rated accuracy after a full-scale step function is applied to its input.
ad7679 rev. 0 | page 12 of 28 typical perf orm ance cha r acte ristics code 2.5 0 6556 11072 196608 2621 inl-lsb 18-bit 1.5 1.0 0 2.5 0.5 0.5 0085-0-005 1.0 2.0 2.0 1.5 f i gure 5 . integr a l no nli n ea ri t y vs . c o d e code in he 70000 counts 50000 30000 0 20000 10000 40000 1febe 1febd 1fec0 1fec1 1fec2 1fec3 1fec4 1fec5 1fec6 v ref = 5v 60000 0 0 0 0 03085-0-006 73 7584 58510 59001 4616 264 f i g u re 6. his t og r a m of 1 31, 0 7 2 co nvers i ons of a dc input a t the code t r a n si t i on positive inl (lsb) 100 0 numbe r of units 60 20 0 40 80 0.5 1.0 1.5 2.0 03085-0-007 2.5 f i gur e 7 . t y pi c a l p o si ti v e inl d i str i but i o n ( 4 24 uni t s) code 2.0 0 65536 131072 196608 26214 4 dnl-ls b (1 8 - bi t) 1.5 1.0 0 1.0 0.5 0.5 03085-0-008 f i gur e 8 . d i ffe r e ntia l no nl inea ri t y vs . c o de code in he 90000 counts 60000 40000 20000 0 30000 10000 50000 1febf 1febe 1fec0 1fec1 1fec2 1fec3 1fec4 1fec5 1fec6 v ref = 5v 70000 80000 0 59 799 2 0 22496 23080 3838 03085-0-009 f i g u re 9. his t og r a m of 1 31, 0 7 2 co nvers i ons of a dc input a t the code c e nt er neative inl (lsb) 120 2.5 numbe r of units 80 60 20 0 2.0 1.5 1.0 0.5 03085-0-010 100 40 0 f i gure 1 0 . t y pi c a l nega ti v e i n l di stri b u ti o n ( 4 24 un i t s)
ad7679 rev. 0 | page 13 of 28 positive dnl (lsb) 120 0 numbe r of units 100 60 20 0 40 80 0.5 1.0 1.5 03085-0-011 2.0 f i gur e 1 1 . t y pi c a l p o si ti v e dnl d i str i b u ti o n ( 4 24 uni t s) neative dnl (lsb) 180 1.00 numbe r of units 160 100 20 0 60 140 0.75 0.50 0.25 03085-0-014 0 120 40 80 f i gure 1 2 . t y pi c a l nega ti v e dnl d i stri b u ti o n ( 4 24 un i t s) frequency (khz) 0 0 3 0 6 0 240 270 amp l itude (db of full s c a l e ) 40 60 100 180 80 120 03085-0-012 140 20 160 90 120 150 180 210 f s = 570ksps f in = 10khz v ref = 4.096v snr = 98.5db thd = 115.8db sfdr = 117.4db s/(n+d) = 98.4db f i g u re 13. fft (1 0 k h z t o n e ) frequency (khz) 105 1 s nr and s / [n+d] (db) 100 90 80 75 85 10 100 1000 03085-0-015 95 enob s/(n+d) snr 16.5 17.0 15.5 16.0 14.5 15.0 14.0 enob ( b it s) fi g u r e 1 4 . s n r , s / ( n + d ) , a n d e n o b v s . fr e q u e n c y frequency (khz) 6 0 1 thd, harmonics (db) 7 0 100 130 120 8 0 10 100 1000 03085-0-016 9 0 110 thd third harmonic sfdr 140 60 20 40 0 s f dr (db) 120 80 100 second harmonic f i gure 15. thd , sf dr, and h a r m onic s vs. f r equenc y input level (db) 60 s nr re fe rre d to full s cale (db) 98 96 100 03085-0-017 snr 50 0 1 0 2 0 3 0 40 102 v ref = 4.096v s/(n+d) f i gure 16. snr and s/(n+d) vs. input l e vel
ad7679 rev. 0 | page 14 of 28 55 s nr, s / [n+d] (db) 98 96 03085-0-018 99 97 3 5 125 85 65 5 15 100 snr enob 14.5 15.0 15.5 16.5 16.0 s/(n+d) 25 45 105 temperature (
ad7679 r. 0 p 15 28 circuit i n formation in ref refgnd in msb c 2c c c lsb s sitches contr o l 262,1c 11, 072c msb c 2c c c lsb s bu s y output code cnst contr ol logic comp 262,1c 11, 072c 0085 0 025 f i 2 . adc si i i s ti t ad7679 i t , , i - , i 18- i t -t - i i t t ad c i i i t i i t t . conerter operation t ad7679 i i i t i ad c i t i t i d a c . f i 2 t i i i t i t ad c. t i t i d a c i t t i ti 18 i i t i t t t t t t t t i t. t ad7679 i i t i i i t t t - a d c . i t t t i t i i t t , i t i i i t t t , i t t i i t i t t - a d c . di t i i t i , t i t ti t t t i t t t a g n d i s s . a i t i t t t t i t . t , t i t i i t i t i in in i t. t ii t i i t t cn s t i t , i i ii t i t . t i i , s s i t. t t i t t i t t i t t t t refgnd i t. t , t i t i t t t in i n i t t t t t ii t i i i t t t i t, i t t t . b i t i t t i t t r e f g nd re f , t t i t i i i t t t ref 2, ref ... ref 2621. t t i t t i t , t t i i t t ms b i t, t i t t k i t i t i. a t ti t i , t t i t t ad c t t i t b u s y t t . t ad7679 i t i t - i t k , i i t i ad c t t t i i t i i t , ki i t i t i t i i t i . t ad7679 t i 5 i t t i t 5 i i t i . i t i i 8- l fp , ti 8- lfcs p t t i i i t i i t i i t . t ad7679 i i -t - i t i i t t ad767, ad7676, ad7678.
ad7679 tra n sfer f u nctions e x cep t in 18-b i t in t e r f ace m o de , th e ad7679 o f f e rs s t ra ig h t b i na r y a nd tw o s co m p le m e n t o u t p u t c o di n g w h en usin g ob/ 2c . s e e f i gur e 24 and t a b l e 8 fo r t h e i d e a l t r a n sfer cha r ac t e r i s t ic. 000...000 000...001 000...010 111...101 111...110 111...111 analog input + f s ? 1.5 lsb + f s ? 1 lsb ?fs + 1 lsb ?fs ? fs + 0.5 lsb adc code (s tra i ght bina ry ) 03085-0-026 f i g u re 24. a d c ide a l t r ans f er f u nc t i o n ta ble 8. out p ut codes a n d i d ea l input volt a g es description analo g input v re f = 4.0 96 v straight binary (hex) twos complement (hex) fsr ?1 lsb 4.095962 v 3ffff 1 1 f f f f 1 fsr ? 2 lsb 4.095924 v 3fffe 1fffe mids cal e + 1 lsb 31.25 v 20001 00001 midscale 0 v 20000 00000 mids cal e ? 1 lsb ?31.25 v 1ffff 3ffff ?fsr + 1 lsb -4.095962 v 00001 20001 ? f s r - 4 . 0 9 6 v 00000 2 2 0 0 0 0 2 1 this is al so the c o de fo r overrange anal og input ( v in + ? v in ? above v re f ? v re f g nd ). 2 this is al so the c o de fo r underrange analog input (v in + ? v in ? below ?v re f + v re f g nd ). av d d a gnd dgnd dv d d ov d d ognd cnvst bu s y sdout sclk rd cs reset pd 2.5v ref no te 1 refbufin 20 ? ? ? ? ? ?
ad7679 typical connection diagram f i gur e 25 s h o w s a typ i cal co nn e c tio n dia g ram f o r th e ad7679. d i f f e r e n t c i rc u i t r y show n o n t h i s d i ag r a m i s opt i on a l a n d i s dis c uss e d la ter i n t h is da t a sh e e t . analog inputs f i g u r e 2 6 s h o w s a s i m p l i f i e d a n al og i n p u t sect io n o f th e ad7679. th e dio d es sh o w n in f i gur e 26 p r o v ide es d p r o t ecti o n f o r th e in p u t s . c a r e m u s t be ta k e n t o e n s u r e th a t t h e a n alog in p u t sig n al ne v e r exce e d s th e abs o l u te ra tin g s on th es e in p u ts. this wi l l ca us e t h es e dio d es t o b e com e fo r w a r d b i as e d a nd st a r t co nd u c t i n g c u r r en t. t h es e dio d es can ha nd le a f o r w a r d-b i as e d c u r r en t o f 120 ma max. this c o n d i t ion co u l d e v en t u al l y o c c u r w h e n t h e i n p u t b u f f er ? s u1 o r u2 s u p p lies a r e d i ff e r e n t fr o m a v d d . i n s u c h a c a s e , a n i n p u t b u ff e r w i t h a sh o r t-cir c ui t c u r r en t limi t a t i on ca n b e us e d t o pr o t e c t t h e p a r t . in+ in? a gnd av d d r+ = 102 ? ? ? ? ?
ad7679 rev. 0 | page 18 of 28 u2 8.25k ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = + ? ? ?
ad7679 rev. 0 | page 19 of 28 sampling ra te (sps) 1000000 pow e r d i ssa pa tion (
ad7679 r. 0 p 20 28 digi tal in t e rface t ad7679 t i i i t i t i t i t i t t t t i i t i i t . t i i t i t i t t . t ad7679 i i t i t t t 5 i i t i t ad7679 o dd i t t t t i t i i t . f i , i t ob 2c i t i i t 18- i t i t , t t t t i t i i . t t i , cs rd , t t i t . t t t i i i , t i t t t i i i . u , cs t t i ad7679 i t ii i t i t i , i i i ad7679 i . rd i t t i t t t . t 9 reset data bus busy cnst t 8 0085-0-05 f i . r e se t ti i cnst busy data bus cs r d 0 preious conersion data n e data t 1 t 10 t t t 11 0085-0-06 f i . m t p d t ti i r i ct i r parallel interf ace t ad7679 i i t t i t i t 18- i t, 16- i t, 8- i t i t , i t t 7. t t i t t i , i i i t t ii t i , i t i i , i fi 5 f i 6 , t i . t t i i t i , , i t i t t i t i i t i t t i . t i i t t i t t t t i t t i i t i t t t i t i i i i t . r t t 7 t i i t i t i t t i i . data bus t 12 t 1 busy cs rd current conersion 0085-0-07 f i 5. s p d t ti i r i r t c t cs 0 cnst , rd t 1 preious conersion data bus t 12 t 1 busy t t 0085-0-08 f i 6. s p d t ti i r i r i c t cs rd a0, a1 pins d158 pins d70 hi- hi- high byte lo byte lo byte high byte hi- hi- t 12 t 12 t 1 0085-0-09 f i 7. 8-b i t 16- bit p it serial interface t ad7679 i i t t i i t m o d e 0 mo d e 1 i . t ad76 79 t t 18 i t t , ms b i t, t s d o u t i . ti t i i i t t 1 8 k i t s c l i . t t t t i i t t i i i t t k .
ad7679 master serial interface i n r e a d d u ri n g c o n v e r s i o n m o d e , th e se ri al c l o c k a n d da ta t o g g l e a t a p p r o p r i a t e in s t a n ts, minimizi n g p o ten t i al fe e d t h r o u g h bet w een d i g i tal a c ti vi t y a n d cri t i c al co n v e r s i o n d e ci s i o n s . inter n al cloc k the ad7679 is co nf igur ed t o gen e r a t e and p r o v ide t h e s e r i al da ta c l ock sc lk w h en th e ex t / int p i n is h e l d lo w . th e ad7679 als o g e n e ra t e s a s y n c sig n al t o indic a te t o th e h o s t w h en t h e s e r i al da t a is v a lid . the s e r i al clo c k s c lk and t h e s y nc sig n al can b e in v e r t e d if desir e d . dep e ndin g o n the rd c/ s d in i n pu t, t h e da t a can b e r e ad a f t e r e a ch con v ersio n or d u r i ng t h e f o l l o w i n g c o n v e r s i on . f i g u re 3 8 an d f i g u re 3 9 show th e d eta ile d ti mi n g di a g ra m s o f th e s e t w o m o d e s . i n r e a d a f t e r c o n v e r s i o n m o d e , i t s h o u l d be n o t e d tha t u n l i k e in o t h e r mo des, t h e b u s y sig n al r e t u r n s lo w a f t e r t h e 18 da t a b i ts a r e p u ls e d ou t an d n o t a t t h e end o f t h e con v ersio n phas e , w h ich r e su lts i n a lo n g er b u s y wi d t h. t o acco mmo d a te s l o w dig i t a l hos t s, th e s e r i al clo c k can b e s l o w ed do wn b y usin g d i v s clk. u s ual l y , be ca us e th e ad7679 is us ed wi t h a fas t thr o u g h p u t, t h e m o de mas t er r e ad d u r i n g co n v er sio n is th e m o st r e co mm en de d se ri al m o d e . t 3 busy cs, r d cnvst sync sclk sdout 12 3 1 6 1 7 1 8 d17 d16 d2 d1 d0 x ext/int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 14 t 20 t 15 t 16 t 22 t 23 t 29 t 28 t 18 t 19 t 21 t 30 t 25 t 24 t 26 t 27 03085-0-040 f i gure 38. mas t e r s e ri al d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) rev. 0 | page 21 of 28
ad7679 rdc/sdin = 1 invsclk = invsync = 0 d17 d16 d2 d1 d0 x 12 3 1 6 1 7 1 8 busy sync sclk s dout cs, rd cnvst t 3 t 1 t 17 t 14 t 15 t 19 t 20 t 21 t 16 t 22 t 23 t 24 t 27 t 26 t 25 t 18 ext/int = 0 03085-0-041 f i g u re 39. m a s t e r s e ri al d a t a tim i ng f o r r e adi n g (r ead pr ev i o us convers i on duri ng co nve r t ) slave serial interface extern al c l oc k the ad7679 is co nf igur ed t o accep t an ext e r n al l y s u p p lied s e r i a l da t a clo c k o n t h e scl k p i n w h e n t h e e x t/ int pi n i s h e l d hig h . i n this m o de , s e veral m e t h o d s can b e us ed t o r e ad t h e da t a . the ext e r n al s e r i al clo c k is ga t e d b y cs . w h e n cs and rd a r e bo th lo w , t h e da t a can be r e ad a f t e r each co n v er sio n o r d u r i n g t h e fol l o w i n g con v ersio n . th e ext e r n al clo c k can b e e i t h e r a c o n t i n u o u s or a d i s c on t i n u ou s cl o c k . a d i s c on t i n u ou s c l o c k can b e ei t h er n o r m al l y hig h o r n o r m al l y lo w wh en i n a c ti v e . f i g u r e 40 a n d f i g u r e 41 s h o w t h e d eta i l ed ti m i n g d i a g ra m s o f th ese m e th od s . w h ile t h e ad7 679 is p e r f o r mi n g a b i t decision, i t is im p o r t an t t h a t v o l t a g e t r an sien ts n o t o c c u r o n dig i t a l in p u t/o u t p ut p i ns o r deg r ad a t ion o f t h e con v ersion r e su l t co u l d o c c u r . this is p a r t ic u l a r ly im p o r t a n t d u r i n g t h e s e con d half o f t h e con v ersio n p h as e bec a us e t h e ad7679 p r o v ides er r o r co r r ec tio n cir c ui tr y th a t ca n co rr ect f o r a n i m p r o p er b i t deci s i o n ma d e d u ri n g t h e f i r s t h a l f of t h e c o n v e r s i on ph a s e. f o r t h i s re a s on , it i s r e co mme n d e d t h a t w h en an exter nal clo c k is b e in g p r o v ide d , i t is a dis c o n tin u o u s c l o c k tha t t o g g l es o n l y wh en b u s y is lo w o r , m o r e im po r t a n t l y , th a t i t doe s n o t tra n s i ti o n d u ri n g th e la t t e r ha lf o f b u s y hi g h . extern al discontinuous clo c k data read after conv ersion this m o de is t h e m o s t r e commen de d o f t h e s e r i al sla v e m o des. f i g u r e 40 s h o w s th e d eta ile d tim i n g dia g ra m s o f th i s m e t h o d . a f te r a c o n v e r s i on i s c o m p l e te, i n d i c a te d b y b u s y re t u r n i n g lo w , th e r e s u l t o f this co n v er sio n can be r e ad w h ile bo t h cs and rd a r e lo w . d a t a is s h if t e d o u t m s b f i rs t wi t h 18 clo c k p u ls es, a nd is va li d o n t h e r i sin g and fa l l in g e d ge o f t h e clo c k. am o n g t h e ad v a n t a g es o f t h is m e t h o d , t h e con v ersio n p e r f o r ma n c e is n o t deg r ade d b e ca us e t h er e a r e n o v o l t a g e t r a n sien ts on t h e dig i t a l i n t e r f ac e d u r i n g t h e con v ersio n p r o c e ss. als o , da t a can b e r e ad a t s p eeds u p t o 40 mh z, acco mm o d a t in g b o t h s l o w dig i t a l h o s t i n t e r f ace a nd t h e fast es t s e r i al r e ading. f i nal l y , in this m o de o n l y , the ad7679 p r o v ides a da isy-c h a i n fe a t ur e usin g t h e rd c / s d in in p u t p i n t o cas c ade m u l t i p le co n v er t e rs t o g e t h er . this fe a t ur e is us ef u l fo r r e d u cin g co m p on e n t co u n t and w i r i n g c o nn e c t i o n s w h e n desir e d ( f o r in st an c e , in is ol a t e d m u lt icon v e r t er a p plica t io ns). an exa m ple o f t h e conca t ena t ion o f tw o de vi ces is s h o w n i n f i gur e 42. s i m u l t a n eo us s a m p lin g is p o s s ib le b y usin g a co mm o n cnv s t sig n al. i t s h o u ld b e n o t e d t h a t t h e r d c/s d i n in p u t is l a t c h e d o n t h e e d ge o f sclk o p p o si t e t h e on e us e d t o s h if t o u t da t a on s d o u t . th us , t h e ms b o f t h e u p s t r e a m co n v er t e r fol l o w s t h e ls b o f t h e down s t r e am co n v er t e r o n t h e ne x t s c l k c y cl e. rev. 0 | page 22 of 28
ad7679 rev. 0 | page 23 of 28 sclk sdout d17 d16 d1 d0 d15 x17 x 1 6 x15 x1 x0 y17 y16 busy sdin invsclk = 0 x17 x 1 6 x 12 3 1 7 1 8 1 9 2 0 ext/ int = 1 r d = 0 t 35 t 36 t 37 t 31 t 32 t 34 t 16 t 33 cs 03085-0-042 f i gure 40. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead a f te r co n v e r t) sdout sclk d1 d0 x d17 d16 d15 12 3 1 7 1 8 busy invsclk = 0 ext/int = 1 r d = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 3 cs cnvst 03085-0-043 f i gure 41. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead p r e v ious con v ers i on d u ring con v e r t)
ad7679 bu s y bu s y ad7679 #2 (upstream) ad7679 #1 (do wnstream) rdc/sdin sdout cnvst cs sclk rdc/sdin sdout cnvst cs sclk da t a out sclk in cs in cnvst in bu s y out 03085-0-044 f i g u re 42. t w o a d 7 6 7 9 s in a d a is y- ch ain conf ig ur at i o n extern al cloc k dat a r e ad during con v e r sion f i g u r e 41 s h o w s th e d eta ile d tim i n g dia g ra m s o f th i s m e t h o d . duri n g a co n v er si o n , wh ile bo t h cs an d rd a r e lo w , t h e r e s u l t o f t h e p r e v io us co n v ersio n can b e r e ad . th e da t a is s h if t e d ou t ms b f i rs t w i t h 18 clo c k p u ls es, a nd is vali d o n b o t h t h e r i sin g a nd fal l in g edg e o f th e c l o c k. the 18 b i ts ha ve t o be r e ad bef o r e t h e c u r r en t con v ersio n is co m p let e . i f t h a t is n o t do ne , rd err o r is p u ls ed hig h an d ca n be us e d t o in t e r r u p t th e h o st in t e r f ace t o p r e v en t i n com p lete da t a r e ading. th er e is n o da isy - cha i n fe a t ur e i n t h is m o de, an d t h e r d c / s d in i n p u t sh o u l d al wa ys b e tie d ei th er hig h o r lo w . t o r e d u ce p e r f o r ma n c e deg r ada t io n d u e t o dig i t a l ac t i v i ty , a fast d i s c on t i n u ou s c l o c k i s re c o m m e n d e d to e n su re t h a t a l l bit s are r e ad d u r i n g t h e f i rs t half o f t h e co n v ersio n phas e . i t is als o p o ss ibl e to b e g i n to re ad t h e d a t a af te r c o n v e r s i on and c o n t i n u e t o r e ad t h e las t b i ts e v e n a f t e r a ne w con v ersio n has b e en ini t i a t e d . microprocessor interfacing the ad7679 is ideal l y s u i t e d f o r tradi t io nal dc m e as ur em en t a p pl i c a t i o ns supp or t i ng a m i c r o p ro c e ss or , an d f o r a c s i g n a l p r oce s si n g a p p l ica t i o n s in t e rfa c in g t o a di gi tal sign al p r oce s so r . the ad7679 is desig n e d t o in t e r f ace ei ther wi t h a p a ral l e l 8-b i t o r 16-b i t wide in t e r f ace , o r wi t h a g e n e ral-p u r p os e s e r i al p o r t o r i/o p o r t s o n a micr o c o n t r ol ler . a va r i ety o f ext e r n al b u f f ers ca n be us e d wi t h the ad7679 t o p r ev en t dig i tal n o is e f r o m co u p ling in t o t h e ad c. th e fol l o w in g s e c t io n i l l u s t ra t e s t h e us e o f t h e ad7679 wi t h an s p i e q ui p p e d ds p , the ads p -219x. spi interface ( a dsp-219x) f i gur e 43 s h o w s a n in t e r f ace diag ra m betw e e n t h e ad7679 and th e s p i eq u i p p e d ads p -219x. t o acco mm o d a t e th e s l o w er s p ee d o f th e ds p , th e ad7679 ac ts as a sla v e de vice , and da ta m u s t b e r e ad a f ter co n v ersio n . this m o de als o al lo ws t h e da isy- cha i n fe a t ur e. t h e con v er t co m m a nd co u l d b e i n i t ia te d in re sp ons e to an i n te r n a l t i me r i n te r r upt . the 1 8 - b it output d a t a a r e r e ad wi t h 3- b y t e s p i acce s s . the r e adi n g p r o c es s co u l d b e ini t i a te d i n r e sp o n s e to t h e e nd- o f -co n version si g n a l ( b us y g o in g lo w) usin g a n i n t e r r u p t li n e o f t h e dsp . th e s e r i al in t e r f ace (spi) o n t h e a d s p -21 9 x is co nf igur e d fo r mast er m o de (mstr) = 1, c l o c k p o la r i ty b i t (c po l) = 0, c l o c k p h as e b i t (cp h a) = 1, a nd s p i in ter r u p t ena b le ( t imo d ) = 00, b y wr i t i n g t o t h e sp i c o n t r o l r e g i st er (s p i cl tx). i t s h o u l d b e n o te d t h a t t o me et al l t i min g r e q u ir em e n ts, t h e s p i clo c k sh o u l d be limi ted t o 17 mb i t s/s, w h ic h al lo w i t t o r e ad a n ad c r e s u l t in ab out 1 . 1 s . whe n a h i g h e r s a m p l i ng r a te i s d e s i re d, u s e of on e of t h e p a r a l l el i n te r f ac e mo de s i s re c o mme nde d . ad7679* adsp-219x* ser/par pfx misox sckx pfx or tfsx bu s y sdout sclk cnvst ext/int cs rd invsclk dv d d * additional pins omitted for clarity spixsel (pfx) 03085-0-045 f i g u re 43. inte r f a c i n g t h e a d 7 6 7 9 to a n spi inte r f ace rev. 0 | page 24 of 28
ad7679 rev. 0 | page 25 of 28 application hints layout the ad7679 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7679 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7679, or at least as close to the ad7679 as possible. if the ad7679 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close to the ad7679 as possible. the user should avoid running digital lines under the device, as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7679 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7679 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7679 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed close to and ideally right up against each power supply pin (avdd, dvdd, and ovdd) and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7679 can be a separate supply or can come from the analog supply, avdd, or the digital interface supply, ovdd. when the system digital supply is noisy or when fast switching digital signals are present, and if no separate supply is available, the user should connect the dvdd digital supply to the analog supply avdd through an rc filter, (see figure 25), and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7679 has four different ground pins: refgnd, agnd, dgnd, and ognd. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. the decoupling capacitor should be close to the adc and should be connected with short and large traces to minimize parasitic inductances. evaluating the ad7679s performance a recommended layout for the ad7679 is outlined in the documentation of the eval-ad7679cb evaluation board for the ad7679. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval- control brd2 .
ad7679 r. 0 p 26 28 outline dimensions top view (pins down ) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc s q seating plane 1.60 ma x 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.10 ma x coplanarity view a rotated 90 ccw seating plane 7 3.5 0 10 6 2 0.15 0.05 compliant to jedec standards ms-026bbc f i g u re 44. 4 8 -l ead l o w p r of i l e q u ad f l at pack [l qf p ] (st - 48) (di m ensio n s sho w n i n mi ll im et er s) pin 1 indicator to p view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 botto m view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 nom 1.00 0.90 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 ma x pin 1 indicator coplanarity 0.08 sq seating plane compliant to jedec standards mo-220-vkkd-2 paddle connected to agnd. this connection is not required to meet the electrical performance f i gure 45. 4 8 -l ead l e adfr a m e chip s c al e p a ck age [lfcs p ] (cp - 4 8 ) (di m ensio n s sho w n i n mi ll im et er s) esd caution esd (ele ctrostati c discharge) sensitive device. elect r osta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detec t i o n. al though this produc t features proprietary esd protec tion c i rc uitry, permanent damage may oc c u r on de vices subjected to hig h energy ele c tros tatic discharges. therefore, prope r esd precautio n s are recommended to av oid performance degradation or loss of functiona l ity. ordering guide model temperature r a nge package descri ption package option ad7 679 ast ?40c to + 85c quad flatpac k (l qfp) st- 48 ad7 679 astrl ?40c to + 85c quad flatpac k (l qfp) st- 48 ad7 679 acp ?40c to + 85c lead frame chip scale (lfcs p ) cp-4 8 ad7 679 acprl ?40c to + 85c lead frame chip scale (lfcs p ) cp-4 8 eval- a d 7679c b 1 e v a l u a t i o n b o a r d eval-con trol brd2 2 c o n t r o l l e r b o a r d 1 th i s boa r d ca n b e u s ed a s a st a n da l o n e eva l ua t i on boa r d o r i n con j u n c t i on wi th t h e ev al- c on tr ol br d 2 fo r eva l ua t i on /dem on st ra t i on purpose s . 2 th i s boa r d a l l o ws a pc t o con t r o l a n d c o m m u n i ca t e wi t h all an a l og d e vi ce s e v a l ua t i on boa r ds e n di n g i n t h e cb de s i gn a t ors.
ad7679 rev. 0 | page 27 of 28 notes
ad7679 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . c03085C0 C 7/03(0) rev. 0 | page 28 of 28

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